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| Data Sheet STEREO 2W AUDIO POWER AMPLIFIER General Description The AA4002 is a monolithic stereo audio power amplifier including DC volume control, a selectable gain/bass boost, and stereo bridged audio power amplifiers, with the capability of producing 2W into 4 with THD+N less than 1%. The AA4002 is specially designed for Notebook PC, LCD monitor and portable media player. The AA4002 features low power consumption in shutdown mode, power amplifier and headphone mute for maximum system flexibility and performance. It also provides thermal shutdown protection. The AA4002 is available in TSSOP-28 with ExposedDAP package. AA4002 Features * * * * * * * * DC Volume Control Interface, 0dB to -78dB, 31 Steps System Beep Detect Very Low Power Consumption in Shutdown Mode, ISD=0.7A Stereo Power Output for Speakers/Headphones with BTL Mode/SE Mode Selectable Internal/External Gain Bass Boost Pop Noise Suppression Circuit Thermal Shutdown Protection Applications * * * * * Notebook PC LCD monitor Portable DVD Player Portable Media Player Digital Photo Frame TSSOP-28 with Exposed-DAP Figure 1. Package Type of AA4002 Sep. 2006 Rev. 1. 1 1 BCD Semiconductor Manufacturing Limited Data Sheet STEREO 2W AUDIO POWER AMPLIFIER Pin Configuration G Package (TSSOP-28 with Exposed-DAP) AA4002 GND SHUTDOWN GAIN SELECT MODE MUTE VDD DC VOL GND RIGHT DOCK RIGHT IN BEEP IN LEFT IN LEFT DOCK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RIGHT OUT+ VDD RIGHT OUTRIGHT GAIN 2 RIGHT GAIN 1 GND BYPASS HP SENSE GND LEFT GAIN 1 LEFT GAIN 2 LEFT OUTVDD LEFT OUT+ Figure 2. Pin Configuration of AA4002 Sep. 2006 Rev. 1. 1 2 BCD Semiconductor Manufacturing Limited Data Sheet STEREO 2W AUDIO POWER AMPLIFIER Pin Description Pin Number 1, 8, 14, 20, 23 2 3 4 5 6, 16, 27 7 9 10 11 12 13 15 17 18 19 21 22 24 25 26 28 Pin Name GND SHUTDOWN GAIN SELECT MODE MUTE VDD DC VOL RIGHT DOCK RIGHT IN BEEP IN LEFT IN LEFT DOCK LEFT OUT+ LEFT OUTLEFT GAIN 2 LEFT GAIN 1 HP SENSE BYPASS RIGHT GAIN 1 RIGHT GAIN 2 RIGHT OUTRIGHT OUT+ Ground for circuitry. Shutdown mode control signal input, place entire IC in shutdown mode when held high, IDD=0.7A. Gain select input pin, logic high will switch the amplifier to external gain mode, and logic low will switch to internal unity gain. Mode select input pin, fixed gain when logic L and gain adjustable mode when logic H. Mute control input pin, active H. Supply voltage input pin. Volume control function input pin. Right docking output pin. Right channel audio input pin. Beep signal input pin. Left channel audio input pin. Left docking output pin. Left channel positive output pin. Left channel negative output pin. Connect pin 2 of the external gain setting resistor for left channel. Connect pin 1 of the external gain setting resistor for left channel. Headphone sense control pin. Bypass pin. Connect pin 1 of the external gain setting resistor for right channel. Connect pin 2 of the external gain setting resistor for right channel. Right channel negative output pin. Right channel positive output pin. Function AA4002 Sep. 2006 Rev. 1. 1 3 BCD Semiconductor Manufacturing Limited Data Sheet STEREO 2W AUDIO POWER AMPLIFIER Functional Block Diagram AA4002 GAIN SELECT 3 LEFT DOCK 13 LEFT GAIN 1 19 LEFT GAIN 2 18 Mute Mode HP Sense 5 4 Mode Control 10k _ 17 21 10k LEFT OUT- DC VOL 7 + 20k 20k LEFT IN 12 _ _ + 15 BEEP IN 11 Beep Detect + Bias Volume Control 31 Steps LEFT OUT+ Bias + 10 RIGHT IN 2 _ + _ 28 RIGHT OUT+ SHUTDOWN 20k VDD 6, 16, 27 20k Power Management 10k + _ 26 RIGHT OUT- GND 1, 8, 14, 20, 23 Bypass 22 Click and Pop Suppression Circuitry 10k 9 24 25 RIGHT DOCK RIGHT GAIN 1 RIGHT GAIN 2 Figure 3. Functional Block Diagram of AA4002 Sep. 2006 Rev. 1. 1 4 BCD Semiconductor Manufacturing Limited Data Sheet STEREO 2W AUDIO POWER AMPLIFIER Truth Table for Logic Inputs (Note 1) Gain Sel 0 0 0 0 1 1 1 1 X X Mode 0 0 1 1 0 0 1 1 X X Headphone Sense 0 1 0 1 0 1 0 1 X X Mute 0 0 0 0 0 0 0 0 1 X Shutdown 0 0 0 0 0 0 0 0 0 1 Output Stage Set To Internal Gain Internal Gain Internal Gain Internal Gain External Gain External Gain External Gain External Gain Muted Shutdown DC Volume Fixed Fixed Adjustable Adjustable Fixed Fixed Adjustable Adjustable X X Output Stage Configuration BTL SE BTL SE BTL SE BTL SE Muted X AA4002 Note 1: If system beep is detected on the BEEP IN pin, the system beep will be passed through the bridged amplifier regardless of the logic of the MUTE and HP SENSE pins. Ordering Information AA4002 Circuit Type Package E1: Lead Free TR: Tape and Reel Blank: Tube G: TSSOP-28 with Exposed-DAP Package Temperature Range Part Number Marking ID Packing Type TSSOP-28 with Exposed-DAP AA4002G-E1 -40 to 85 AA4002GTR-E1 AA4002G-E1 AA4002G-E1 Tube Tape & Reel BCD Semiconductor's Pb-free products, as designated with "E1" suffix in the part number, are RoHS compliant. Sep. 2006 Rev. 1. 1 5 BCD Semiconductor Manufacturing Limited Data Sheet STEREO 2W AUDIO POWER AMPLIFIER Absolute Maximum Ratings (Note 2) Parameter Supply Voltage Input Voltage Power Dissipation ESD (Machine Model) Operating Junction Temperature Storage Temperature Symbol VDD VIN PD ESD TJ TSTG Value 6.0 -0.3 to VDD + 0.3 Internally limited 200 (Note 3) 150 -65 to 150 V oC oC oC oC/W AA4002 Unit V V Lead Temperature (Soldering 10s) Package Thermal Resistance TL RJA (Note 4) 260 45 Note 2: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operation is not implied. Exposure to "Absolute Maximum Ratings" for extended periods may affect device reliability. Note 3: This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Note 4: The Chip is soldered to 200mm2 copper of 1oz. with 12x0.5mm vias. Recommended Operating Conditions Parameter Supply Voltage Operating Temperature Symbol VDD TA Min 2.7 -40 Max 5.5 85 Unit V oC Sep. 2006 Rev. 1. 1 6 BCD Semiconductor Manufacturing Limited Data Sheet STEREO 2W AUDIO POWER AMPLIFIER Electrical Characteristics (VDD=5V, TA=25oC, unless otherwise specified.) Parameter Standby and Logical Section Supply Voltage Quiescent Power Supply Current Shutdown Current Headphone Sense High Input Voltage Headphone Sense Low Input Voltage (Mute, Shutdown, Mode, Select) High Input Voltage (Mute, Shutdown, Mode, Select) Low Input Voltage Volume Attenuators Section Attenuator Range CRANGE VVOL=5V (DC), No load VVOL=0V (DC), BTL and SE Mode VMUTE=5V, BTL Mode VMUTE=5V, SE Mode THD=1%, f=1kHz, RL=32 THD=10%, f=1kHz, RL=32 -75 -78 -78 0.75 dB dB dB dB Gain Gain VDD IDD ISD VIH VIL VIH VIL 3 1 VIN=0V, IOUT=0A VSHUTDOWN=VDD 4 0.8 2.7 11 0.7 5.5 30 2.0 V mA A V V V V Symbol Conditions Min Typ Max Unit AA4002 Mute Attenuation Single-ended (SE) Mode Section AM 85 95 0.065 58 102 65 mW % dB dB dB Output Power Total Harmonic Distortion + Noise Power Supply Rejection Ratio Signal to Noise Ratio Channel Separation BTL Mode Section Output Offset Voltage POUT THD+N VOUT=1VRMS, f=1kHz, RL=10K, AVD=1 PSRR SNR CB=1.0F, f=120kHz, RL=32, VRIPPLE=200mVRMS POUT=75mW, RL=32, A-Wtd Filter f=1kHz, CB=1.0F VOS VIN=0V, No load THD+N=1%, f=1kHz, RL=4, LPF=22kHz 5 2 50 mV W Output Power POUT THD+N=1%, f=1kHz, RL=8, THD+N=10%, f=1kHz, RL=8, 1.0 1.1 1.5 0.3 74 % dB Total Harmonic Distortion + Noise Power Supply Rejection Ratio THD+N POUT=1.0W, RL=4, AVD=2 20Hz BCD Semiconductor Manufacturing Limited Data Sheet STEREO 2W AUDIO POWER AMPLIFIER Electrical Characteristics (Continued) (VDD=5V, TA=25oC, unless otherwise specified.) Parameter BTL Mode Section (Continued) Signal to Noise Ratio Channel Separation SNR POUT=1.1W, RL=8, A-Wtd Filter CB=1.0F, f=1kHz 93 70 dB dB Symbol Conditions Min Typ Max Unit AA4002 Typical Performance Characteristics 10 VDD=5V SE Mode RL=33 LPF=80KHz 10 VDD=5V BTL Mode RL=3.9 LPF=80KHz THD+N (%) THD+N (%) 1 1KHz 20KHz 20Hz 1 0.1 0.01 1KHz (COUT=220F) 20KHz (COUT=220F) 20Hz (COUT=1000F) 10 Output Power (mW) 100 0.1 100m 1 Output Power (W) Figure 4. THD+N vs. Output Power Figure 5. THD+N vs. Output Power 10 VDD=5V BTL Mode RL=8.2 LPF=80KHz 1KHz 20KHz 20Hz 0 -20 VDD=5V SE Mode CB=1.0F VRIPPLE=200mVRMS THD+N (%) PSRR (dB) 100m 1 -40 1 -60 -80 0.1 -100 10m 20 100 1k 10k 20K Output Power (W) Frequency (Hz) Figure 6. THD+N vs. Output Power Figure 7. PSRR vs. Frequency Sep. 2006 Rev. 1. 1 8 BCD Semiconductor Manufacturing Limited Data Sheet STEREO 2W AUDIO POWER AMPLIFIER Typical Performance Characteristics (Continued) AA4002 10 VDD=5V SE Mode RL=33 Po=75mW COUT=1000F LPF=80KHz 1 VDD=5V BTL Mode RL=3.9 Po=1.5W LPF=30KHz THD+N (%) 1 0.1 THD+N (%) 0.1 100 1k 10k 20 20 100 1k 10k Frequency (Hz) Frequency (Hz) Figure 8. THD+N vs. Frequency Figure 9. THD+N vs. Frequency 160 SE Mode f=1KHz RL=33 THD=1% LPF=80KHz 160 SE Mode f=1KHz RL=33 THD=10% LPF=80KHz 140 140 Output Power (mW) 120 Output Power (mW) 3.5 4.0 4.5 5.0 5.5 120 100 100 80 80 60 60 40 40 20 2.5 3.0 20 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Supply Voltage (V) Supply Voltage (V) Figure 10. Output Power vs. Supply Voltage Figure 11. Output Power vs. Supply Voltage Sep. 2006 Rev. 1. 1 9 BCD Semiconductor Manufacturing Limited Data Sheet STEREO 2W AUDIO POWER AMPLIFIER Typical Performance Characteristics (Continued) AA4002 1.8 1.6 1.4 BTL Mode RL=8.2 f=1KHz THD=1% 2.2 2.0 1.8 BTL Mode RL=8.2 f=1KHz THD=10% Output Power (W) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.5 Output Power (W) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 2.5 3.0 3.5 4.0 4.5 5.0 5.5 3.0 3.5 4.0 4.5 5.0 5.5 Supply Voltage (V) Supply Voltage (V) Figure 12. Output Power vs. Supply Voltage Figure 13. Output Power vs. Power Supply 700 650 600 550 VDD=5V SE Mode f=1KHz LPF=80KHz 2.4 2.2 2.0 1.8 VDD=5V BTL Mode f=1KHz LPF=80KHz THD+N=1% THD+N=10% Output Power (mW) 500 450 400 350 300 250 200 150 100 50 0 8.0 16.0 24.0 32.0 40.0 48.0 Output Power (W) THD+N=1% THD+N=10% 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 56.0 64.0 0.0 8.0 16.0 24.0 32.0 40.0 48.0 56.0 64.0 Load Resistance () Load Resistance () Figure 14. Output Power vs. Load Resistance Figure 15. Output Power vs. Load Resistance Sep. 2006 Rev. 1. 1 10 BCD Semiconductor Manufacturing Limited Data Sheet STEREO 2W AUDIO POWER AMPLIFIER Typical Performance Characteristics (Continued) AA4002 0.26 0.24 0.22 VDD=5V SE Mode f=1KHz THD<1% LPF=80KHz 1.8 1.6 VDD=5V BTL Mode f=1KHz RL=3.9 Power Dissipation (W) 0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.0 Power Dissipation (W) AA4002 RL=8 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0 AA4002 RL=33 40.0m 80.0m 120.0m 160.0m 200.0m 0.5 1.0 1.5 2.0 2.5 Output Power (W) Output Power (W) Figure 16. Power Dissipation vs. Output Power Figure 17. Power Dissipation vs. Output Power 20 18 16 0 VIN=0mV IO=0mA -10 -20 Supply Current (mA) 14 12 BTL Mode 10 8 6 4 -70 2 0 2.5 -80 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 SE Mode Attenuation (dB) 4.5 5.0 5.5 -30 -40 -50 -60 3.0 3.5 4.0 Supply Voltage (V) Volume Control Voltage (V) Figure 18. Supply Current vs. Supply Voltage Figure 19. Volume Control Characteristics Sep. 2006 Rev. 1. 1 11 BCD Semiconductor Manufacturing Limited Data Sheet STEREO 2W AUDIO POWER AMPLIFIER Typical Performance Characteristics (Continued) AA4002 -40 VDD=5V SE Mode RL=33 f=1KHz CB=1F 12.0 10.0 CBS=0.068F CBS=0.1F Channel Separation (dB) -50 8.0 Output Level (dB) -60 6.0 CBS=0.22F 4.0 -70 2.0 VDD=5V RL=8.2 RI=RBS=RF=20K 50 100 200 300 500 1K 2K 5K 10K 20K -80 20 100 1k 10k 0.0 20 Frequency (Hz) Frequency (Hz) Figure 20. Channel Separation vs. Frequency Figure 21. External Gain/Bass Boost Characteristics Sep. 2006 Rev. 1. 1 12 BCD Semiconductor Manufacturing Limited Data Sheet STEREO 2W AUDIO POWER AMPLIFIER Application Information SE/BTL Mode, HP_SENSE Pin The AA4002 can be operated in 2 types of output configurations, SE (Single-Ended) mode and BTL (Bridged-Tied-Load) mode, determined by HP_SENSE pin (pin 21) logic level. (Here is the discussion about left channel only, it also applies to right channel.) AA4002 28, RPU=100k, RL=1.5k, DC voltage at HP_SENSE is about 75mV. AC signal equals output amplitude of OUT- through COUT, so signal at HP_SENSE node is 75mV DC plus AC signal. The maximum Peak-toPeak voltage at OUT- is not greater than VDD=5.0V supply voltage, so the positive maximum voltage of HP_SENSE node is not greater than 2.5V+75mV=2.575V, which can not reach HP_SENSE input high level minimum value (4.0V), there is no risk of mode switching between SE and BTL. HP_SENSE pin can also be connected to MCU I/O port, it is necessary to note that AA4002 still can drive headphone even in BTL mode because OUT- is always active whatever SE or BTL mode. 10k _ + 20k 10k COUT 220F + Left Out- 17 20k _ RL 1.5k OP1 Internal/External Gain, Gain SELECT Pin Left Out+ 15 Bias + OP2 Figure 22. BTL Configuration in Left Channel If applying high level to pin 21, the output of OP2 unit is in high impedance, the chip operates in SE mode. There is no current loop between OUT+ and OUT-, also no power consumption. When HP_SENSE pin is held low, OP2 unit is turned on, the chip operates in BTL mode. AC signal at OUT+ is -180o phase shift of OUT-. OP2 has fixed unity gain internally, so DC components (Bias voltage, approx 1/2 VDD) between OUT+, OUT- is canceled. There is no need for DC block capacitors in system. In BTL mode, voltage between speaker load is about 2 times that in SE mode, so there is 4 times output power compared to SE mode with same load. In SE mode, output audio signal rides on Bias voltage at OUT-, so it is necessary to use capacitor to block DC bias and couple AC signal. See Figure 28 typical application circuit. It is recommended to connect HP_SENSE to the control pin of headphone jack, illustrated in Figure 28. When headphone plug is not inserted, the voltage of HP_SENSE pin is determined by voltage divider formed by RPU, RL. For given resistors value in Figure Sep. 2006 Rev. 1. 1 13 The AA4002 provides 2 selectable feedback loops, Internal and External determined by SELECT pin (pin 3) logic level. Applying low level to SELECT pin, the AA4002 switches to internal feedback loop, OP1 works as unity gain. If applying high level to SELECT pin, external components are used as feedback loop, and the gain is expressed by formula below. AVFB = ( RBS // ZC BS ) + RF ..............................(1) RI Here ZCBS is the impedance of bass boost capacitor, ZCBS=1/2*f*CBS. So AVFB approaches 2 points, AVFBLF at low frequency, AVFBHF at high frequency, expressed by formula 2 and 3. AVDLF = AVFBHF = RBS + RF .............................................(2) RI RF ........................................................(3) RI Bass Boost From above discussion, the AA4002 can improve gain of audio signal at low frequency, which is hard to listening for human ears relative to middle band (2kHz to 3kHz). The boost corner frequency is determined by formula 4. BCD Semiconductor Manufacturing Limited Data Sheet STEREO 2W AUDIO POWER AMPLIFIER Application Information (Continued) f BS = 1 2RBS C BS ..............................................(4) Assuming RBS=RF=RI=20k, CBS=0.068F and fBS=117Hz, the bass boost characteristic is shown in Figure 21. Attenuation (dB) 0 -1 -2 -3 -4 -5 -6 -8 -10 -12 -14 AA4002 Table 1. Volume Attenuation vs. DC VOL Pin Voltage VDD=5V High Level (V) 5 3.937 3.812 3.687 3.562 3.437 3.312 3.187 3.06 2.937 2.812 2.687 2.562 2.437 2.312 2.187 2.062 1.937 1.812 1.687 1.562 1.437 1.312 1.187 1.062 0.937 0.812 0.687 0.562 0.437 0.312 Low Level (V) 3.875 3.750 3.625 3.500 3.375 3.250 3.125 3.000 2.875 2.750 2.625 2.500 2.375 2.250 2.125 2.000 1.875 1.750 1.625 1.500 1.375 1.250 1.125 1.000 0.875 0.750 0.625 0.500 0.375 0.250 0 Fixed Gain/Adjustable Gain Loop, MODE pin, DC Volume Control The AA4002 can be set in fixed gain or adjustable gain, according to applying high or low level to MODE pin (pin 4). Low level is for fixed gain, High level is for adjustable gain, which permits to change volume by applying various DC voltages to DC VOL pin (pin7). Table 1 shows the relationship of Volume Attenuation vs. the voltage of DC VOL pin. There are 31 steps from 0 to -78dB; step size is different for different volume control voltage, 1dB/step from 0dB to -6dB, 2dB/step from -6dB to -36dB, 3dB/step from -36dB to -47dB, 4dB/step from -47db to -51dB, 5dB/step from -51dB to -66dB, The last step is 12dB from -66dB to -78dB. -16 -18 -20 -22 -24 -26 -28 -30 -32 -34 -36 -39 -42 -45 -47 -51 Figure 23. Volume Attenuation vs. DC VOL Pin Voltage -56 -61 For example, increasing voltage applied to DC VOL pin from 3.437V (point B in Figure 23) to 3.562V (point D), gain will change one step from -4dB to -3dB (point F). Sep. 2006 Rev. 1. 1 14 -66 -78 BCD Semiconductor Manufacturing Limited Data Sheet STEREO 2W AUDIO POWER AMPLIFIER Application Information (Continued) But, decreasing voltage from 3.562V (point F), gain does not change immediately, the change occurs at 3.5V (point E). There is a hysteresis which guarantees that the volume control is monotonic, with immunity against noise coupled from system. In above Table 1, the column of Low Level means the lower threshold voltage with the voltage of DC VOL varying from high to low, High Level column means the other upper threshold voltage DC VOL voltage varying from low to high. AA4002 fixed gain, ignoring MUTE and HP_SENSE pin logic level. For AA4002, VDETECT is about 2.8V. Beep signal passes through Left/Right channel input path, the gain under BTL load is only dependent on the ratio of RF(L/R) to RBEEP. AVBEEP ( L / R ) = 2 RF ( L / R ) RBEEP .................................(6) Mute, Shutdown When applying high level to MUTE pin (pin 5), the AA4002 will mute output stage stereo dock outputwhatever in BTL or SE mode. The AA4002 offers shutdown function which can further reduce power consumption. SHUTDOWN pin (pin 2) should be held low in normal operation. If applying high level to SHUTDOWN pin, the AA4002 will turn off internal bias circuits, enter into shutdown mode with very low quiescent current, 0.7A Typ. MUTE, SHUTDOWN pin should be tied to high or low level to avoid undesired operation state. For resistors value given in Figure 28, AVBEEP is about 0.2 (-14dB). If this feature is not used, connecting the capacitor (CBEEP) to ground, it is recommended removing two resistors (RBEEP, 200k), to minimize crosstalk between left and right channel. CI, COUT, CB and CS (Power Supply Bypassing Capacitor) Selection For input stages of Left/Right channel, input capacitors (CIL, CIR), are used to accommodate different DC level between input source and AA4002 bias voltage (about 1/2 VDD). Input capacitors (CIL, CIR) and input resistors (RIL, RIR) form first order High Pass Filters, which determine the corner frequency, Left/Right Dock Output There are stereo amplifiers built-in AA4002 front-end input stages. It provide very low distortion audio monitor signal for line out, the pass-band gain is determined by external feedback resistors, f CI ( L / R ) = 1 ..........................(7) 2RI ( L / R ) C I ( L / R ) AVDOCK ( L / R ) = RF ( L / R ) RI ( L / R ) .....................................(5) For given values in Figure 28, RIL=RIR=20k, CIL=CIR=0.33F, the corner frequency of input stage is about 24Hz. Similarly, for output stage in SE mode, output capacitor (COUT), and headphone load also form a first order High Pass Filter, and its cut-off frequency is determined by classic formula below. The dock output is also used as input source for backend amplifiers, so the gain of docking output (AVDOCK) will affect total loop gain. The function of COUT(L/R) (0.1F) serial in Left/Right dock output is to remove DC bias. f CO ( L / R ) = 1 2RHP ( L / R ) CO ( L / R ) ....................(8) Beep Detect Beep feature is used in Notebook PC system for alerting. If peak-to-peak voltage of beep signal applied to BEEP DETECT pin (pin 11) exceeds a certain voltage called detect voltage, the feature will be activated, then AA4002 will be forced at BTL mode with internal Sep. 2006 Rev. 1. 1 15 For bypass capacitor (CB), the purpose is to filter internal bias noise, reduce harmonic distortion, and improve power supply rejection ratio performance. Tantalum or ceramic capacitor with low ESR is recommended, and is placed as close as possible to chip bypass pin in PCB layout. Both input and output BCD Semiconductor Manufacturing Limited Data Sheet STEREO 2W AUDIO POWER AMPLIFIER Application Information (Continued) signal ride on such reference voltage, the chip can not work until internal DC bias is set up completely. So the size of CB can also affect the chip start-up time, which is approx linearly proportional to the value of bypass capacitor. For AA4002, here are the start-up times for several typical capacitor values. Table 2. CB vs. Start-up Time CB (F) 0.47 1.0 2.2 Start-up Time (ms) 300 600 1300 AA4002 According to formulas above, it is easy to plot Amplitude-Frequency characteristic curve. The lower corner frequency is dependant on AVIN, AVOUT, Bass Boost feature relies on AVOUT. Example VDD=5V, RL=8, BTL configuration, desired output power each channel, PO=1.0W, THD+N 1%. Input signal, VIN=1.0VRMS from D-A converter. Step 1, To check if the chip can deliver 1W to 8 load with the limitation of THD+N 1%, VDD=5V by Figure 6, 15. Step 2, If yes, to calculate output voltage, . So total pass-band gain (ignoring Bass boost feature, low frequency attenuation caused by AC coupling capacitors, AVFB=1x.), AVTOTAL=VOUT/VIN=2.83x. Step 3, AVIN=AVTOTAL/( AVFB*AVOUT )=2.83/(1*2)=1.415, RF(L/R)=AVIN*RI(L/R), assuming components values are given in Figure 28, just changing RF(L/R) to 20k*1.415=28.3k. Select the closest standard value 28k. For AA4002 power supply, it is better to use individual power source generated from voltage regulators split from video, digital circuit units in system. For bypassing capacitors, it is recommended to use one electrolytic capacitor of 4.7F to 10F in parallel with 0.1F ceramic capacitor which is located close to the part. Setup Proper Gain, Design Example The total closed loop gain is determined by three individual units - input stage, feedback network and output stage. Input stage, pass-band gain Optimizing CLICK/POP Noise The AA4002 includes a circuit to suppress CLICK/ POP noise during power up/down transition. In practical application, the chip can effectively suppress common mode signal including CLICK/POP noise in BTL configuration. In SE mode, decreasing the size of output capacitor (COUT) can minish POP noise, which can also affect low frequency response according to formula 8 above. Increasing bypass capacitor value (CB) can slower ramp of charge, prolong start-up time, mask most of transient noises before bias voltage is set-up. Proper power on/off sequence can also optimize CLICK/POP noise. The recommended is shown in Figure 24. AVIN = RF ( L / R ) RI ( L / R ) ...................................................(9) Feedback network, Internal pass-band gain, AVFB=1, for external gain, see formula 1, 2, 3. Output stage, for BTL mode, AVOUT=2, for SE mode, AVOUT=1. So the total pass-band gain of AA4002, AVTOTAL is, AVTOTAL = AVIN AVFB AVOUT ........................(10) Sep. 2006 Rev. 1. 1 16 BCD Semiconductor Manufacturing Limited Data Sheet STEREO 2W AUDIO POWER AMPLIFIER Application Information (Continued) VDD(V) (pin6,16,27) AA4002 TJMAX is maximum operating junction Here temperature 150oC, TA is ambient temperature, JA is thermal resistance form junction to ambient. For G package (TSSOP-28 with exposed DAP), it is 45oC/W given in datasheet page 6. Assuming TA is +25oC, the maximum allowed power dissipation PDMAX is about 2.78W according to formula 12. There is the other formula about power dissipation drawn from application for each channel which is determined by supply voltage and load resistance. Mute(V) (pin5) Shutdown(V) (pin2) OFF STBY MUTE PLAY PDSEMAX MUTE STBY OFF V (for SE mode)....................(13) = DD 2 2 RL 2V = 2DD (for BTL mode).................(14) RL 2 2 Figure 24. Recommended Sequences for Power ON/OFF PDBTLMAX 1) Power ON operation, enable mute, then enable shutdown; after VDD is stable, release shutdown first, then mute. 2) Power OFF, enable mute, then enable shutdown; after VDD is discharged completely, release shutdown firstly, then mute. If power dissipation calculated by application is larger than permissible by package, it is necessary to assemble additional heat sinking, or keep ambient temperature around the chip very low, or increasing load impedance, or decreasing power supply voltage. Here is an example, assuming VDD=5.0V, RL=4, stereo in BTL mode, Efficiency, Power Dissipation and Thermal Consideration in Design For Class-AB amplifier, Figure 11 is the basic equation of efficiency worked in BTL configuration, PDBTLMAX = = VP 4VDD 2VDD 2 x 52 = = 1.266W 2 RL 3.14 2 x 4 2 ........................................................(11) Here VP is peak voltage of output swing. Thermal dissipation becomes major concern when output power is close to 2W especially in BTL mode. The maximum power dissipation of package for AA4002 can be calculated by following equation. , for 2 channels, total power dissipation PDTOTAL=2* PDBTLMAX=2*1.266=2.53W, according to formula 13, the maxim ambient temperature is, TA = TJMAX - JA PDBTLMAX =150-45*2.53=36.2 oC That is to say, if user wants AA4002 can delivery maximum output power to 4 load, at VDD=5.0V, BTL mode, ambient temperature has to hold less than 36.2oC. When junction temperature exceeds about +165oC, thermal shutdown circuit built-in AA4002 BCD Semiconductor Manufacturing Limited 17 PDMAX = TJMAX - TA JA ........................................(12) Sep. 2006 Rev. 1. 1 Data Sheet STEREO 2W AUDIO POWER AMPLIFIER Application Information (Continued) will turn off output stage to limit total power dissipation. AA4002 and make sure to keep them contact well when soldering to PCB. See Figure 24. Recommended PCB Layout for AA4002 There is an exposed thermal pad on bottom of the chip to provide the direct thermal path from die to external heat sink. It is recommended to use copper on the surface of PC Board as heat sink for AA4002. To dig some matrix regular holes under chip, set diameter for each hole at 0.8~1.0mm, keep distance around 1.7mm between holes, remove copper solder mask of this area, Using wide traces for power supply, output power to reduce losses caused by parasitic resistance is recommended, which can also help to release heat away from the chip. It is recommended to place bypass capacitor, power supply bypassing capacitors as close as possible to the chip. Figure 25, 26 shows the recommended layout of double layer PCB. Figure 25. Copper and Holes under the Chip Figure 26. Top Route, Copper and Silkscreen Sep. 2006 Rev. 1. 1 18 BCD Semiconductor Manufacturing Limited Data Sheet STEREO 2W AUDIO POWER AMPLIFIER Application Information (Continued) AA4002 Figure 27. Bottom Route, Copper and Silkscreen Sep. 2006 Rev. 1. 1 19 BCD Semiconductor Manufacturing Limited Data Sheet STEREO 2W AUDIO POWER AMPLIFIER Typical Application VDD VDD VDD CV 0.1F RPU 100k DC Volume Control RW 10k 3 Gain Select 7 DC Vol 19 Left Gain 1 RI 20k RF 20k AA4002 18 Left Gain 2 RBS 20k CBS 0.068F To Control Pin on Headphone Jack RS 100k 21 HP Sense 5 4 COUTL 0.1F + 13 Left Dock Mute Mode Mode Control Left Dock Audio In Left RIL 20k 10k _ 10k COUT 220F + Left Out- 17 RL 1.5k CONTROL PIN _ PIN RING To HP Sense Circuit CIL 0.33F RBEEP 200k RFL 20k 12 Left In _ + Beep Detect + 10 Right In _ Bias Volume Control 31 Steps Bias + 20k 20k BEEP In + Audio In Right RIR 20k + 11 Beep In + Left Out+ 15 Right Out+ RBEEP 200k + RFR 20k 9 Right Dock + _ 28 TIP CIR 0.33F SLEEVE 20k 20k 6, 16, 27 VDD Power Management + _ 1, 8, 14, 20, 23 GND 10k 10k 22 Bypass CB 1F Click and Pop Suppression Circuitry RBS 20k CBS 0.068F Right Out - 26 + COUT 220F Right Dock COUTR 1F HEADPHONE JACK RL 1.5k + CS1 10F CS 0.1F CS 0.1F Shutdown 2 Right Gain 1 24 Right Gain 2 25 RI 20k RF 20k Figure 28. Typical Application of AA4002 Sep. 2006 Rev. 1. 1 20 BCD Semiconductor Manufacturing Limited Data Sheet STEREO 2W AUDIO POWER AMPLIFIER Mechanical Dimensions TSSOP-28 with Exposed-DAP 9.600(0.378) 9.800(0.386) AA4002 Unit: mm(inch) 6.250(0.246) 6.550(0.258) BASE PLANE PIN #1 ID. 1.200(0.047)MAX 0.800(0.032) 1.050(0.041) GAUGE LINE 0.250(0.010) 4.300(0.169) 4.500(0.177) 0 8 0.190(0.007) 0.300(0.012) 0.050(0.002) 0.150(0.006) 0.450(0.018) 0.750(0.030) 0.090(0.004) 0.200(0.008) SEATING PLANE 0.650(0.026) BSC EXPOSED PAD 2.740(0.108) 3.050(0.120) 5.640(0.222) 5.940(0.234) Sep. 2006 Rev. 1. 1 21 BCD Semiconductor Manufacturing Limited http://www.bcdsemi.com IMPORTANT NOTICE BCD Semiconductor Manufacturing Limited reserves the right to make changes without further notice to any products or specifications herein. BCD Semiconductor Manufacturing Limited does not assume any responsibility for use of any its products for any particular purpose, nor does BCD Semiconductor Manufacturing Limited assume any liability arising out of the application or use of any its products or circuits. BCD Semiconductor Manufacturing Limited does not convey any license under its patent rights or other rights nor the rights of others. MAIN SITE BCD Semiconductor Manufacturing Limited - Wafer Fab Shanghai SIM-BCD Semiconductor Manufacturing Limited 800, Yi Shan Road, Shanghai 200233, China Tel: +86-21-6485 1491, Fax: +86-21-5450 0008 BCD Semiconductor Manufacturing Limited - IC Design Group Advanced Analog Circuits (Shanghai) Corporation 8F, Zone B, 900, Yi Shan Road, Shanghai 200233, China Tel: +86-21-6495 9539, Fax: +86-21-6485 9673 REGIONAL SALES OFFICE Shenzhen Office Shanghai SIM-BCD Semiconductor Manufacturing Co., Ltd. Shenzhen Office Advanced Analog Circuits (Shanghai) Corporation Shenzhen Office Room E, 5F, Noble Center, No.1006, 3rd Fuzhong Road, Futian District, Shenzhen 518026, China Tel: +86-755-8826 7951, Fax: +86-755-8826 7865 Taiwan Office BCD Semiconductor (Taiwan) Company Limited 4F, 298-1, Rui Guang Road, Nei-Hu District, Taipei, Taiwan Tel: +886-2-2656 2808, Fax: +886-2-2656 2806 USA Office BCD Semiconductor Corporation 3170 De La Cruz Blvd., Suite 105, Santa Clara, CA 95054-2411, U.S.A |
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